Altium

Design Rule Verification Report

Date:		5/6/2025
Time:		1:22:15 PM
Elapsed Time:		00:00:02
Filename:		C:\Users\Public\Documents\Altium\ESC-BLDC\BLDC_ESC.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=6mil) (All),(All)	0
Clearance Constraint (Gap=8mil) (InNetClass('POWER_OUT') or InNet('PVDD')),(All)	0
Short-Circuit Constraint (Allowed=Yes) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=8mil) (Max=60mil) (Preferred=24mil) (InNet('PVDD')or InNetClass('POWER_OUT') or InNet('GND'))	0
Width Constraint (Min=10mil) (Max=16mil) (Preferred=10mil) (InNet('+3V3'))	0
Width Constraint (Min=8mil) (Max=12mil) (Preferred=8mil) (All)	0
Width Constraint (Min=12mil) (Max=20mil) (Preferred=20mil) (InNetClass('MID_POWER') or InNet('VBUS'))	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0